{"id":33141,"date":"2024-05-23T14:18:19","date_gmt":"2024-05-23T14:18:19","guid":{"rendered":"https:\/\/express24.ir\/d\/product\/%da%a9%d8%aa%d8%a7%d8%a8-%d8%a8%d8%b1%d9%86%d8%a7%d9%85%d9%87-%d9%86%d9%88%db%8c%d8%b3%db%8c-fpga-%d8%a8%d8%b1%d8%a7%db%8c-%d9%85%d8%a8%d8%aa%d8%af%db%8c%d8%a7%d9%86%d8%9b-%d8%a7%d8%ad%db%8c%d8%a7\/"},"modified":"2024-05-23T10:58:44","modified_gmt":"2024-05-23T10:58:44","slug":"%da%a9%d8%aa%d8%a7%d8%a8-%d8%a8%d8%b1%d9%86%d8%a7%d9%85%d9%87-%d9%86%d9%88%db%8c%d8%b3%db%8c-fpga-%d8%a8%d8%b1%d8%a7%db%8c-%d9%85%d8%a8%d8%aa%d8%af%db%8c%d8%a7%d9%86%d8%9b-%d8%a7%d8%ad%db%8c%d8%a7","status":"publish","type":"product","link":"https:\/\/express24.ir\/d\/product\/%da%a9%d8%aa%d8%a7%d8%a8-%d8%a8%d8%b1%d9%86%d8%a7%d9%85%d9%87-%d9%86%d9%88%db%8c%d8%b3%db%8c-fpga-%d8%a8%d8%b1%d8%a7%db%8c-%d9%85%d8%a8%d8%aa%d8%af%db%8c%d8%a7%d9%86%d8%9b-%d8%a7%d8%ad%db%8c%d8%a7\/","title":{"rendered":"\u06a9\u062a\u0627\u0628 \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc FPGA \u0628\u0631\u0627\u06cc \u0645\u0628\u062a\u062f\u06cc\u0627\u0646\u061b \u0627\u062d\u06cc\u0627\u06cc \u0627\u06cc\u062f\u0647 \u0647\u0627 \u0628\u0627 \u0633\u0627\u062e\u062a \u0637\u0631\u062d \u0647\u0627\u06cc \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631\u06cc \u0648 \u0645\u062f\u0627\u0631\u0647\u0627\u06cc \u0627\u0644\u06a9\u062a\u0631\u0648\u0646\u06cc\u06a9\u06cc \u0628\u0627 SystemVerilog"},"content":{"rendered":"

 <\/p>\n

\"\u062f\u0627\u0646\u0644\u0648\u062f<\/div>\n\n\n\n
\n

\u0639\u0646\u0648\u0627\u0646 \u06a9\u062a\u0627\u0628 \u0628\u0647 \u0627\u0646\u06af\u0644\u06cc\u0633\u06cc:<\/h3>\n<\/td>\n

\n

FPGA Programming for Beginners: Bring your ideas to life by creating hardware designs and electronic circuits with SystemVerilog<\/h3>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n
\u0633\u0627\u0644 \u0627\u0646\u062a\u0634\u0627\u0631: 2021\u00a0\u00a0|\u00a0\u00a0368 \u0635\u0641\u062d\u0647\u00a0\u00a0|\u00a0\u00a0\u062d\u062c\u0645 \u0641\u0627\u06cc\u0644: 16 \u0645\u06af\u0627\u0628\u0627\u06cc\u062a\u00a0\u00a0|\u00a0\u00a0\u0632\u0628\u0627\u0646: \u0627\u0646\u06af\u0644\u06cc\u0633\u06cc<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n
\u0646\u0648\u06cc\u0633\u0646\u062f\u0647<\/td>\nFrank Bruno<\/td>\n<\/tr>\n
\u0646\u0627\u0634\u0631<\/td>\nPackt Publishing<\/td>\n<\/tr>\n
ISBN10:<\/td>\n1789805414<\/td>\n<\/tr>\n
ISBN13:<\/td>\n9781789805413<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u062a\u0648\u0636\u06cc\u062d\u0627\u062a \u06a9\u062a\u0627\u0628<\/h2>\n
Get started with FPGA programming using SystemVerilog, and develop real-world skills by building projects, including a calculator and a keyboard
\nKey FeaturesExplore different FPGA usage methods and the FPGA tool flow
\nLearn how to design, test, and implement hardware circuits using SystemVerilog
\nBuild real-world FPGA projects such as a calculator and a keyboard using FPGA resourcesBook Description<\/p>\n

Field Programmable Gate Arrays (FPGAs) have now become a core part of most modern electronic and computer systems. However, to implement your ideas in the real world, you need to get your head around the FPGA architecture, its toolset, and critical design considerations. FPGA Programming for Beginners will help you bring your ideas to life by guiding you through the entire process of programming FPGAs and designing hardware circuits using SystemVerilog.<\/p>\n

The book will introduce you to the FPGA and Xilinx architectures and show you how to work on your first project, which includes toggling an LED. You’ll then cover SystemVerilog RTL designs and their implementations. Next, you’ll get to grips with using the combinational Boolean logic design and work on several projects, such as creating a calculator and updating it using FPGA resources. Later, the book will take you through the advanced concepts of AXI and serial interfaces and show you how to create a keyboard using PS\/2. Finally, you’ll be able to consolidate all the projects in the book to create a unified output using a Video Graphics Array (VGA) controller that you’ll design.<\/p>\n

By the end of this SystemVerilog FPGA book, you’ll have learned how to work with FPGA systems and be able to design hardware circuits and boards using SystemVerilog programming.
\nWhat you will learn<\/p>\n

Understand the FPGA architecture and its implementation
\nGet to grips with writing SystemVerilog RTL
\nMake FPGA projects using SystemVerilog programming
\nWork with computer math basics, parallelism, and pipelining
\nExplore the advanced topics of AXI and serial interfaces
\nDiscover how you can implement a VGA interface in your projects<\/p>\n

Who this book is for<\/p>\n

This FPGA design book is for embedded system developers, engineers, and programmers who want to learn FPGA and SystemVerilog programming from scratch. FPGA designers looking to gain hands-on experience in working on real-world projects will also find this book useful.
\nTable of Contents<\/p>\n

Introduction to FPGAs and Xilinx architectures
\nDesigning with combinational logic
\nCounting button presses
\nLet’s build a calculator
\nFPGA resources and how to use them – DSP, RAM, PLLs
\nMath, parallelism, and pipelined design
\nIntroduction to AXI
\nSerial interfaces – SPI, I2C, UART, PS\/2
\nLots of data? MIG and DDR2
\nA better way to display information – VGA
\nAdvanced Topics<\/p>\n<\/div>\n

\u062a\u0648\u0636\u06cc\u062d\u0627\u062a \u06a9\u062a\u0627\u0628 \u0628\u0647 \u0641\u0627\u0631\u0633\u06cc (\u062a\u0631\u062c\u0645\u0647 \u0645\u0627\u0634\u06cc\u0646\u06cc)<\/h2>\n

\u0628\u0627 \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc FPGA \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 SystemVerilog \u0634\u0631\u0648\u0639 \u06a9\u0646\u06cc\u062f \u0648 \u0628\u0627 \u0633\u0627\u062e\u062a \u067e\u0631\u0648\u0698\u0647 \u0647\u0627 \u0627\u0632 \u062c\u0645\u0644\u0647 \u0645\u0627\u0634\u06cc\u0646 \u062d\u0633\u0627\u0628 \u0648 \u0635\u0641\u062d\u0647 \u06a9\u0644\u06cc\u062f \u060c \u0645\u0647\u0627\u0631\u062a \u0647\u0627\u06cc \u062f\u0646\u06cc\u0627\u06cc \u0648\u0627\u0642\u0639\u06cc \u0631\u0627 \u062a\u0648\u0633\u0639\u0647 \u062f\u0647\u06cc\u062f
\n\u0648\u06cc\u0698\u06af\u06cc \u0647\u0627\u06cc \u06a9\u0644\u06cc\u062f\u06cc<\/p>\n

\u0631\u0648\u0634\u0647\u0627\u06cc \u0645\u062e\u062a\u0644\u0641 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 FPGA \u0648 \u062c\u0631\u06cc\u0627\u0646 \u0627\u0628\u0632\u0627\u0631 FPGA \u0631\u0627 \u06a9\u0627\u0648\u0634 \u06a9\u0646\u06cc\u062f
\n\u0646\u062d\u0648\u0647 \u0637\u0631\u0627\u062d\u06cc \u060c \u0622\u0632\u0645\u0627\u06cc\u0634 \u0648 \u067e\u06cc\u0627\u062f\u0647 \u0633\u0627\u0632\u06cc \u0645\u062f\u0627\u0631\u0647\u0627\u06cc \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631\u06cc \u0631\u0627 \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 SystemVerilog \u0628\u06cc\u0627\u0645\u0648\u0632\u06cc\u062f
\n\u0633\u0627\u062e\u062a \u067e\u0631\u0648\u0698\u0647 \u0647\u0627\u06cc FPGA \u062f\u0631 \u062f\u0646\u06cc\u0627\u06cc \u0648\u0627\u0642\u0639\u06cc \u0645\u0627\u0646\u0646\u062f \u0645\u0627\u0634\u06cc\u0646 \u062d\u0633\u0627\u0628 \u0648 \u0635\u0641\u062d\u0647 \u06a9\u0644\u06cc\u062f \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0645\u0646\u0627\u0628\u0639 FPGA<\/p>\n

\u062a\u0648\u0636\u06cc\u062d\u0627\u062a \u06a9\u062a\u0627\u0628<\/p>\n

\u0622\u0631\u0627\u06cc\u0647 \u0647\u0627\u06cc \u062f\u0631\u0648\u0627\u0632\u0647 \u0642\u0627\u0628\u0644 \u0628\u0631\u0646\u0627\u0645\u0647 \u0631\u06cc\u0632\u06cc Field (FPGA) \u0627\u06a9\u0646\u0648\u0646 \u0628\u0647 \u0628\u062e\u0634 \u0627\u0635\u0644\u06cc \u062a\u0631\u06cc\u0646 \u0633\u06cc\u0633\u062a\u0645 \u0647\u0627\u06cc \u0627\u0644\u06a9\u062a\u0631\u0648\u0646\u06cc\u06a9\u06cc \u0648 \u0631\u0627\u06cc\u0627\u0646\u0647 \u0627\u06cc \u0645\u062f\u0631\u0646 \u062a\u0628\u062f\u06cc\u0644 \u0634\u062f\u0647 \u0627\u0646\u062f.\u0628\u0627 \u0627\u06cc\u0646 \u062d\u0627\u0644 \u060c \u0628\u0631\u0627\u06cc \u0627\u062c\u0631\u0627\u06cc \u0627\u06cc\u062f\u0647 \u0647\u0627\u06cc \u062e\u0648\u062f \u062f\u0631 \u062f\u0646\u06cc\u0627\u06cc \u0648\u0627\u0642\u0639\u06cc \u060c \u0628\u0627\u06cc\u062f \u0633\u0631 \u062e\u0648\u062f \u0631\u0627 \u0628\u0647 \u0645\u0639\u0645\u0627\u0631\u06cc FPGA \u060c \u0627\u0628\u0632\u0627\u0631 \u0627\u0628\u0632\u0627\u0631 \u0622\u0646 \u0648 \u0645\u0644\u0627\u062d\u0638\u0627\u062a \u0637\u0631\u0627\u062d\u06cc \u0645\u0647\u0645 \u0628\u062f\u0633\u062a \u0622\u0648\u0631\u06cc\u062f.\u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc FPGA \u0628\u0631\u0627\u06cc \u0645\u0628\u062a\u062f\u06cc\u0627\u0646 \u0628\u0647 \u0634\u0645\u0627 \u06a9\u0645\u06a9 \u0645\u06cc \u06a9\u0646\u062f \u062a\u0627 \u0628\u0627 \u0647\u062f\u0627\u06cc\u062a \u0634\u0645\u0627 \u062f\u0631 \u06a9\u0644 \u0641\u0631\u0622\u06cc\u0646\u062f \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc FPGA \u0648 \u0637\u0631\u0627\u062d\u06cc \u0645\u062f\u0627\u0631\u0647\u0627\u06cc \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631\u06cc \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 SystemVerilog \u060c \u0627\u06cc\u062f\u0647 \u0647\u0627\u06cc \u062e\u0648\u062f \u0631\u0627 \u0632\u0646\u062f\u0647 \u06a9\u0646\u06cc\u062f.<\/p>\n

\u0627\u06cc\u0646 \u06a9\u062a\u0627\u0628 \u0634\u0645\u0627 \u0631\u0627 \u0628\u0627 \u0645\u0639\u0645\u0627\u0631\u06cc \u0647\u0627\u06cc FPGA \u0648 Xilinx \u0622\u0634\u0646\u0627 \u0645\u06cc \u06a9\u0646\u062f \u0648 \u0628\u0647 \u0634\u0645\u0627 \u0646\u0634\u0627\u0646 \u0645\u06cc \u062f\u0647\u062f \u06a9\u0647 \u0686\u06af\u0648\u0646\u0647 \u0645\u06cc \u062a\u0648\u0627\u0646\u06cc\u062f \u0631\u0648\u06cc \u0627\u0648\u0644\u06cc\u0646 \u067e\u0631\u0648\u0698\u0647 \u062e\u0648\u062f \u06a9\u0627\u0631 \u06a9\u0646\u06cc\u062f \u060c \u06a9\u0647 \u0634\u0627\u0645\u0644 \u06cc\u06a9 LED \u0627\u0633\u062a.\u0633\u067e\u0633 \u0637\u0631\u062d \u0647\u0627\u06cc SystemVerilog RTL \u0648 \u067e\u06cc\u0627\u062f\u0647 \u0633\u0627\u0632\u06cc \u0647\u0627\u06cc \u0622\u0646\u0647\u0627 \u0631\u0627 \u067e\u0648\u0634\u0634 \u0645\u06cc \u062f\u0647\u06cc\u062f.\u062f\u0631 \u0645\u0631\u062d\u0644\u0647 \u0628\u0639\u062f \u060c \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0637\u0631\u0627\u062d\u06cc \u0645\u0646\u0637\u0642\u06cc Boolean Logic \u0648 \u062f\u0631 \u0686\u0646\u062f\u06cc\u0646 \u067e\u0631\u0648\u0698\u0647 \u0645\u0627\u0646\u0646\u062f \u0627\u06cc\u062c\u0627\u062f \u0645\u0627\u0634\u06cc\u0646 \u062d\u0633\u0627\u0628 \u0648 \u0628\u0647 \u0631\u0648\u0632\u0631\u0633\u0627\u0646\u06cc \u0622\u0646 \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0645\u0646\u0627\u0628\u0639 FPGA \u06a9\u0627\u0631 \u0645\u06cc \u06a9\u0646\u06cc\u062f.\u0628\u0639\u062f\u0627\u064b \u060c \u0627\u06cc\u0646 \u06a9\u062a\u0627\u0628 \u0634\u0645\u0627 \u0631\u0627 \u0627\u0632 \u0637\u0631\u06cc\u0642 \u0645\u0641\u0627\u0647\u06cc\u0645 \u067e\u06cc\u0634\u0631\u0641\u062a\u0647 \u0631\u0627\u0628\u0637 \u0647\u0627\u06cc AXI \u0648 \u0633\u0631\u06cc\u0627\u0644 \u0628\u0647 \u0634\u0645\u0627 \u0645\u0646\u062a\u0642\u0644 \u0645\u06cc \u06a9\u0646\u062f \u0648 \u0628\u0647 \u0634\u0645\u0627 \u0646\u0634\u0627\u0646 \u0645\u06cc \u062f\u0647\u062f \u06a9\u0647 \u0686\u06af\u0648\u0646\u0647 \u0645\u06cc \u062a\u0648\u0627\u0646\u06cc\u062f \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 PS\/2 \u06cc\u06a9 \u0635\u0641\u062d\u0647 \u06a9\u0644\u06cc\u062f \u0627\u06cc\u062c\u0627\u062f \u06a9\u0646\u06cc\u062f.\u0633\u0631\u0627\u0646\u062c\u0627\u0645 \u060c \u0634\u0645\u0627 \u0642\u0627\u062f\u0631 \u062e\u0648\u0627\u0647\u06cc\u062f \u0628\u0648\u062f \u062a\u0627 \u062a\u0645\u0627\u0645 \u067e\u0631\u0648\u0698\u0647 \u0647\u0627\u06cc \u0645\u0648\u062c\u0648\u062f \u062f\u0631 \u06a9\u062a\u0627\u0628 \u0631\u0627 \u0628\u0631\u0627\u06cc \u0627\u06cc\u062c\u0627\u062f \u06cc\u06a9 \u062e\u0631\u0648\u062c\u06cc \u06cc\u06a9\u067e\u0627\u0631\u0686\u0647 \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u06cc\u06a9 \u06a9\u0646\u062a\u0631\u0644\u0631 \u0622\u0631\u0627\u06cc\u0647 \u06af\u0631\u0627\u0641\u06cc\u06a9\u06cc \u0648\u06cc\u062f\u06cc\u0648\u06cc\u06cc (VGA) \u06a9\u0647 \u0637\u0631\u0627\u062d\u06cc \u062e\u0648\u0627\u0647\u06cc\u062f \u06a9\u0631\u062f \u060c \u0627\u062f\u063a\u0627\u0645 \u06a9\u0646\u06cc\u062f.<\/p>\n

\u0628\u0627 \u067e\u0627\u06cc\u0627\u0646 \u0627\u06cc\u0646 \u06a9\u062a\u0627\u0628 SystemVerilog FPGA \u060c \u0634\u0645\u0627 \u06cc\u0627\u062f \u06af\u0631\u0641\u062a\u0647 \u0627\u06cc\u062f \u06a9\u0647 \u0686\u06af\u0648\u0646\u0647 \u0628\u0627 \u0633\u06cc\u0633\u062a\u0645 \u0647\u0627\u06cc FPGA \u06a9\u0627\u0631 \u06a9\u0646\u06cc\u062f \u0648 \u0628\u062a\u0648\u0627\u0646\u06cc\u062f \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc SystemVerilog \u060c \u0645\u062f\u0627\u0631\u0647\u0627 \u0648 \u062a\u0627\u0628\u0644\u0648\u0647\u0627\u06cc \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631\u06cc \u0631\u0627 \u0637\u0631\u0627\u062d\u06cc \u06a9\u0646\u06cc\u062f.
\n\u0622\u0646\u0686\u0647 \u06cc\u0627\u062f \u062e\u0648\u0627\u0647\u06cc\u062f \u06af\u0631\u0641\u062a<\/p>\n

\u0645\u0639\u0645\u0627\u0631\u06cc FPGA \u0648 \u0627\u062c\u0631\u0627\u06cc \u0622\u0646 \u0631\u0627 \u062f\u0631\u06a9 \u06a9\u0646\u06cc\u062f
\n\u0628\u0627 \u0646\u0648\u0634\u062a\u0646 systemverilog rtl \u0628\u0647 \u062f\u0633\u062a \u0648 \u067e\u0646\u062c\u0647 \u0646\u0631\u0645 \u06a9\u0646\u06cc\u062f
\n\u067e\u0631\u0648\u0698\u0647 \u0647\u0627\u06cc FPGA \u0631\u0627 \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc SystemVerilog \u0627\u0646\u062c\u0627\u0645 \u062f\u0647\u06cc\u062f
\n\u0628\u0627 \u0627\u0635\u0648\u0644 \u0631\u06cc\u0627\u0636\u06cc \u0631\u0627\u06cc\u0627\u0646\u0647 \u0627\u06cc \u060c \u0645\u0648\u0627\u0632\u06cc \u0633\u0627\u0632\u06cc \u0648 \u0644\u0648\u0644\u0647 \u06a9\u0634\u06cc \u06a9\u0627\u0631 \u06a9\u0646\u06cc\u062f
\n\u0645\u0628\u0627\u062d\u062b \u067e\u06cc\u0634\u0631\u0641\u062a\u0647 \u0631\u0627\u0628\u0637 \u0647\u0627\u06cc AXI \u0648 \u0633\u0631\u06cc\u0627\u0644 \u0631\u0627 \u06a9\u0627\u0648\u0634 \u06a9\u0646\u06cc\u062f
\n\u06a9\u0634\u0641 \u06a9\u0646\u06cc\u062f \u06a9\u0647 \u0686\u06af\u0648\u0646\u0647 \u0645\u06cc \u062a\u0648\u0627\u0646\u06cc\u062f \u06cc\u06a9 \u0631\u0627\u0628\u0637 VGA \u0631\u0627 \u062f\u0631 \u067e\u0631\u0648\u0698\u0647 \u0647\u0627\u06cc \u062e\u0648\u062f \u067e\u06cc\u0627\u062f\u0647 \u0633\u0627\u0632\u06cc \u06a9\u0646\u06cc\u062f<\/p>\n

\u0627\u06cc\u0646 \u06a9\u062a\u0627\u0628 \u0628\u0631\u0627\u06cc \u0686\u0647 \u06a9\u0633\u06cc \u0627\u0633\u062a<\/p>\n

\u0627\u06cc\u0646 \u06a9\u062a\u0627\u0628 \u0637\u0631\u0627\u062d\u06cc FPGA \u0628\u0631\u0627\u06cc \u062a\u0648\u0633\u0639\u0647 \u062f\u0647\u0646\u062f\u06af\u0627\u0646 \u0633\u06cc\u0633\u062a\u0645 \u062a\u0639\u0628\u06cc\u0647 \u0634\u062f\u0647 \u060c \u0645\u0647\u0646\u062f\u0633\u0627\u0646 \u0648 \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u0627\u0646 \u0627\u0633\u062a \u06a9\u0647 \u0645\u06cc \u062e\u0648\u0627\u0647\u0646\u062f \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc FPGA \u0648 SystemVerilog \u0631\u0627 \u0627\u0632 \u0627\u0628\u062a\u062f\u0627 \u06cc\u0627\u062f \u0628\u06af\u06cc\u0631\u0646\u062f.\u0637\u0631\u0627\u062d\u0627\u0646 FPGA \u0628\u0647 \u062f\u0646\u0628\u0627\u0644 \u0628\u0647 \u062f\u0633\u062a \u0622\u0648\u0631\u062f\u0646 \u062a\u062c\u0631\u0628\u0647 \u062f\u0633\u062a\u06cc \u062f\u0631 \u06a9\u0627\u0631 \u062f\u0631 \u067e\u0631\u0648\u0698\u0647 \u0647\u0627\u06cc \u062f\u0646\u06cc\u0627\u06cc \u0648\u0627\u0642\u0639\u06cc \u0646\u06cc\u0632 \u0627\u06cc\u0646 \u06a9\u062a\u0627\u0628 \u0631\u0627 \u0645\u0641\u06cc\u062f \u0645\u06cc \u062f\u0627\u0646\u0646\u062f.
\n\u0641\u0647\u0631\u0633\u062a \u0645\u0637\u0627\u0644\u0628<\/p>\n

\u0622\u0634\u0646\u0627\u06cc\u06cc \u0628\u0627 \u0645\u0639\u0645\u0627\u0631\u06cc FPGAS \u0648 Xilinx
\n\u0637\u0631\u0627\u062d\u06cc \u0628\u0627 \u0645\u0646\u0637\u0642 \u062a\u0631\u06a9\u06cc\u0628\u06cc
\n\u062f\u06a9\u0645\u0647 \u0634\u0645\u0627\u0631\u0634 \u0641\u0634\u0627\u0631
\n\u0628\u06cc\u0627\u06cc\u06cc\u062f \u06cc\u06a9 \u0645\u0627\u0634\u06cc\u0646 \u062d\u0633\u0627\u0628 \u0628\u0633\u0627\u0632\u06cc\u0645
\n\u0645\u0646\u0627\u0628\u0639 FPGA \u0648 \u0646\u062d\u0648\u0647 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0622\u0646\u0647\u0627 – DSP \u060c RAM \u060c PLLS
\n\u0631\u06cc\u0627\u0636\u06cc \u060c \u0645\u0648\u0627\u0632\u06cc \u0648 \u0637\u0631\u0627\u062d\u06cc \u062e\u0637 \u0644\u0648\u0644\u0647
\n\u0645\u0642\u062f\u0645\u0647 \u0627\u06cc \u0628\u0631\u0627\u06cc Axi
\n\u0631\u0627\u0628\u0637 \u0647\u0627\u06cc \u0633\u0631\u06cc\u0627\u0644 – SPI \u060c I2C \u060c UART \u060c PS\/2
\n\u062f\u0627\u062f\u0647 \u0647\u0627\u06cc \u0632\u06cc\u0627\u062f\u06cc\u061fMIG \u0648 DDR2
\n\u0631\u0627\u0647\u06cc \u0628\u0647\u062a\u0631 \u0628\u0631\u0627\u06cc \u0646\u0645\u0627\u06cc\u0634 \u0627\u0637\u0644\u0627\u0639\u0627\u062a – VGA
\n\u0645\u0628\u0627\u062d\u062b \u067e\u06cc\u0634\u0631\u0641\u062a\u0647
\n
\r\n\r\n\t\r\n\t\t\r\n\t\t\r\n\t\t\r\n\t\t\r\n\t\t\r\n\t\t
\r\n\t\t\t\r\n\u062a\u0648\u062c\u0647 \u06a9\u0646\u06cc\u062f \u06a9\u0647 \u0627\u06cc\u0646 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0635\u0648\u0631\u062a \u0641\u0627\u06cc\u0644 \u062f\u0627\u0646\u0644\u0648\u062f\u06cc \u0627\u0633\u062a \u0648 \u0646\u0647 \u06a9\u062a\u0627\u0628 \u06a9\u0627\u063a\u0630\u06cc.\r\n\r\n\t\t<\/td>\r\n\t<\/tr>\r\n\r\n\t\t
\r\n\t\t\t\r\n\u0628\u0647 \u0647\u0646\u06af\u0627\u0645 \u062e\u0631\u06cc\u062f \u0628\u0647 \u0632\u0628\u0627\u0646 \u062f\u0631\u062c \u0634\u062f\u0647 \u0628\u0631\u0627\u06cc \u06a9\u062a\u0627\u0628 \u062d\u062a\u0645\u0627 \u062a\u0648\u062c\u0647 \u06a9\u0646\u06cc\u062f. \u0628\u0647 \u0635\u0648\u0631\u062a \u0645\u0639\u0645\u0648\u0644 \u062f\u0631 \u0627\u06a9\u062b\u0631 \u0645\u0648\u0627\u0631\u062f \u0632\u0628\u0627\u0646 \u06a9\u062a\u0627\u0628 \u0641\u0627\u0631\u0633\u06cc \u0646\u06cc\u0633\u062a.\r\n\r\n\t\t<\/td>\r\n\t<\/tr>\t\r\n\r\n\t\t\t
\r\n\t\t\t\r\n\u062f\u0631 \u0635\u0648\u0631\u062a \u0647\u0631\u06af\u0648\u0646\u0647 \u0645\u0634\u06a9\u0644 \u062f\u0631 \u062f\u0631\u06cc\u0627\u0641\u062a \u06a9\u062a\u0627\u0628 \u0628\u0647 \u0634\u0645\u0627\u0631\u0647 09395106248 \u067e\u06cc\u0627\u0645\u06a9 \u062f\u0647\u06cc\u062f. \r\n\t\t<\/td>\r\n\t<\/tr>\t\r\n\t\r\n\t\t\t
\r\n\t\t\t\r\n\u062f\u0631\u062c \u0634\u0645\u0627\u0631\u0647 \u0645\u0648\u0628\u0627\u06cc\u0644 \u0628\u0631\u0627\u06cc \u0633\u0641\u0627\u0631\u0634 \u0636\u0631\u0648\u0631\u06cc \u0646\u06cc\u0633\u062a \u0648\u0644\u06cc \u062a\u0631\u062c\u06cc\u062d \u0622\u0646 \u0627\u0633\u062a \u062f\u0631\u062c \u06af\u0631\u062f\u062f \u062a\u0627 \u062f\u0631 \u0635\u0648\u0631\u062a \u0628\u0631\u0648\u0632 \u0645\u0634\u06a9\u0644 \u0627\u0648\u0644\u06cc\u0646 \u0631\u0627\u0647 \u0627\u0631\u062a\u0628\u0627\u0637\u06cc \u0645\u0627 \u0628\u0627 \u0634\u0645\u0627 \u0628\u0627\u0634\u062f.\r\n\t\t<\/td>\r\n\t<\/tr>\r\n\t\r\n\t
\r\n\t\t\t\r\n\t\t\t\u0686\u0646\u0627\u0646\u0686\u0647 \u062f\u0631 \u062f\u0631\u06cc\u0627\u0641\u062a \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0647\u0631 \u062f\u0644\u06cc\u0644\u06cc \u0628\u0627 \u0645\u0634\u06a9\u0644 \u0631\u0648\u0628\u0631\u0648 \u0634\u062f\u06cc\u062f \u0648 \u0645\u0637\u0645\u0626\u0646 \u0627\u0632 \u067e\u0631\u062f\u0627\u062e\u062a \u0645\u0648\u0641\u0642 \u0648\u062c\u0647 \u0647\u0633\u062a\u06cc\u062f \u0628\u0647 \u0634\u0645\u0627\u0631\u0647 \u062a\u0645\u0627\u0633 \u0632\u06cc\u0631 \u0646\u0627\u0645\u060c \u0646\u0627\u0645 \u062e\u0627\u0646\u0648\u0627\u062f\u06af\u06cc \u0648 \u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0631\u0627 \u067e\u06cc\u0627\u0645\u06a9 \u0628\u0632\u0646\u06cc\u062f \u062a\u0627 \u0644\u06cc\u0646\u06a9 \u0645\u062d\u0635\u0648\u0644 \u0633\u0631\u06cc\u0639\u0627 \u0628\u0631\u0627\u06cc \u0634\u0645\u0627 \u0627\u0631\u0633\u0627\u0644 \u06af\u0631\u062f\u062f.\r\n\t\t\t

\r\n\t\t\t\u0634\u0645\u0627\u0631\u0647 \u062a\u0645\u0627\u0633: 09395106248 \r\n\r\n\t\t<\/td>\r\n\t<\/tr>\r\n\t\r\n<\/table>\r\n
\r\n\r\n<\/p>\n","protected":false},"excerpt":{"rendered":"

  \u0639\u0646\u0648\u0627\u0646 \u06a9\u062a\u0627\u0628 \u0628\u0647 \u0627\u0646\u06af\u0644\u06cc\u0633\u06cc: FPGA Programming for Beginners: Bring your ideas to life by creating hardware designs and electronic […]<\/p>\n","protected":false},"featured_media":33143,"comment_status":"open","ping_status":"closed","template":"","meta":{"pmpro_default_level":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}}},"product_cat":[196,472,468],"product_tag":[],"class_list":{"0":"post-33141","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-196","7":"product_cat-472","8":"product_cat-468","9":"pmpro-has-access","10":"desktop-align-left","11":"tablet-align-left","12":"mobile-align-left","14":"first","15":"instock","16":"shipping-taxable","17":"purchasable","18":"product-type-variable"},"yoast_head":"\n\u06a9\u062a\u0627\u0628 \u0628\u0631\u0646\u0627\u0645\u0647 \u0646\u0648\u06cc\u0633\u06cc FPGA \u0628\u0631\u0627\u06cc \u0645\u0628\u062a\u062f\u06cc\u0627\u0646\u061b \u0627\u062d\u06cc\u0627\u06cc \u0627\u06cc\u062f\u0647 \u0647\u0627 \u0628\u0627 \u0633\u0627\u062e\u062a \u0637\u0631\u062d \u0647\u0627\u06cc \u0633\u062e\u062a \u0627\u0641\u0632\u0627\u0631\u06cc \u0648 \u0645\u062f\u0627\u0631\u0647\u0627\u06cc \u0627\u0644\u06a9\u062a\u0631\u0648\u0646\u06cc\u06a9\u06cc \u0628\u0627 SystemVerilog - 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