{"id":102710,"date":"2025-05-27T20:03:24","date_gmt":"2025-05-27T20:03:24","guid":{"rendered":"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/"},"modified":"2025-05-27T20:03:26","modified_gmt":"2025-05-27T20:03:26","slug":"%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7","status":"publish","type":"product","link":"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/","title":{"rendered":"\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC"},"content":{"rendered":"\n\n\n\n\n\n
\u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0627\u0646\u06af\u0644\u06cc\u0633\u06cc<\/th>\n\u062f\u0627\u0646\u0644\u0648\u062f Introduction to VHDL for FPGA and ASIC design<\/td>\n<\/tr>\n
\u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0641\u0627\u0631\u0633\u06cc<\/th>\n\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC<\/td>\n<\/tr>\n
\u0632\u0628\u0627\u0646<\/th>\n\u0627\u0646\u06af\u0644\u06cc\u0633\u06cc \u0628\u0627 \u0632\u06cc\u0631\u0646\u0648\u06cc\u0633 \u0641\u0627\u0631\u0633\u06cc<\/td>\n<\/tr>\n
\u0646\u0648\u0639 \u0645\u062d\u0635\u0648\u0644<\/th>\n\u0622\u0645\u0648\u0632\u0634 \u0648\u06cc\u062f\u06cc\u0648\u06cc\u06cc<\/td>\n<\/tr>\n
\u0646\u062d\u0648\u0647 \u062a\u062d\u0648\u06cc\u0644<\/th>\n\u0628\u0647 \u0635\u0648\u0631\u062a \u062f\u0627\u0646\u0644\u0648\u062f\u06cc<\/td>\n<\/tr>\n<\/table>\n
\r\n \u062a\u0648\u062c\u0647 \u0645\u0647\u0645:<\/strong>\r\n

\r\n \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647 \u0622\u0645\u0648\u0632\u0634\u06cc \u062f\u0627\u0646\u0644\u0648\u062f\u06cc<\/span> \u0628\u0648\u062f\u0647 \u0648 \u0647\u0645\u0631\u0627\u0647 \u0628\u0627 \u0632\u06cc\u0631\u0646\u0648\u06cc\u0633 \u0641\u0627\u0631\u0633\u06cc<\/span> \u0627\u0631\u0627\u0626\u0647 \u0645\u06cc\u200c\u06af\u0631\u062f\u062f.\r\n <\/p>\r\n

\r\n \u062d\u062f\u0627\u06a9\u062b\u0631 \u062a\u0627 \u06f2\u06f4 \u0633\u0627\u0639\u062a \u067e\u0633 \u0627\u0632 \u0633\u0641\u0627\u0631\u0634<\/strong>\u060c \u0644\u06cc\u0646\u06a9 \u0627\u062e\u062a\u0635\u0627\u0635\u06cc \u062f\u0648\u0631\u0647 \u0628\u0631\u0627\u06cc \u0634\u0645\u0627 \u0633\u0627\u062e\u062a\u0647 \u0648 \u062c\u0647\u062a \u062f\u0627\u0646\u0644\u0648\u062f \u0627\u0631\u0633\u0627\u0644 \u062e\u0648\u0627\u0647\u062f \u0634\u062f.\r\n <\/p>\r\n

\r\n \u062c\u0647\u062a \u067e\u06cc\u06af\u06cc\u0631\u06cc \u0633\u0641\u0627\u0631\u0634\u060c \u0645\u06cc\u200c\u062a\u0648\u0627\u0646\u06cc\u062f \u0627\u0632 \u0637\u0631\u06cc\u0642 \u0648\u0627\u062a\u0633\u200c\u0627\u067e \u0628\u0627 \u0634\u0645\u0627\u0631\u0647 09395106248<\/strong> \u06cc\u0627 \u0622\u06cc\u062f\u06cc \u062a\u0644\u06af\u0631\u0627\u0645\u06cc @ma_limbs<\/strong> \u062f\u0631 \u062a\u0645\u0627\u0633 \u0628\u0627\u0634\u06cc\u062f.\r\n <\/p>\r\n<\/div>\r\n\r\n\n

\n

\u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC<\/h1>\n
\n

\u0645\u0639\u0631\u0641\u06cc \u062f\u0648\u0631\u0647<\/h2>\n

\n \u062f\u0648\u0631\u0647\u0654 \u201c\u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC\u201d<\/span> \u0628\u0627 \u0647\u062f\u0641 \u0622\u0634\u0646\u0627\u06cc\u06cc \u0639\u0645\u06cc\u0642 \u0628\u0627 \u0632\u0628\u0627\u0646 \u062a\u0648\u0635\u06cc\u0641 \u0633\u062e\u062a\u200c\u0627\u0641\u0632\u0627\u0631 VHDL \u0648 \u06a9\u0627\u0631\u0628\u0631\u062f\u0647\u0627\u06cc \u0622\u0646 \u062f\u0631 \u0637\u0631\u0627\u062d\u06cc \u0645\u062f\u0627\u0631\u0647\u0627\u06cc \u062f\u06cc\u062c\u06cc\u062a\u0627\u0644 \u0628\u0631\u0646\u0627\u0645\u0647\u200c\u0631\u06cc\u0632\u06cc \u0634\u062f\u0647 \u0627\u0633\u062a. \u062f\u0631 \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647\u060c \u0641\u0631\u0627\u06af\u06cc\u0631\u0627\u0646 \u0628\u0627 \u0645\u0641\u0627\u0647\u06cc\u0645 \u067e\u0627\u06cc\u0647\u200c\u0627\u06cc \u062a\u0648\u0635\u06cc\u0641 \u0633\u062e\u062a\u200c\u0627\u0641\u0632\u0627\u0631\u06cc\u060c \u0633\u0627\u062e\u062a\u0627\u0631 \u0641\u0627\u06cc\u0644\u200c\u0647\u0627\u06cc VHDL \u0648 \u0646\u062d\u0648\u0647\u0654 \u0645\u062f\u0644\u200c\u0633\u0627\u0632\u06cc \u0628\u0644\u0648\u06a9\u200c\u0647\u0627\u06cc \u0645\u0646\u0637\u0642\u06cc \u0622\u0634\u0646\u0627 \u062e\u0648\u0627\u0647\u0646\u062f \u0634\u062f.\n <\/p>\n

\n \u0628\u0627 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0645\u062b\u0627\u0644\u200c\u0647\u0627\u06cc \u0648\u0627\u0642\u0639\u06cc \u0648 \u067e\u0631\u0648\u0698\u0647\u200c\u0647\u0627\u06cc \u06af\u0627\u0645\u200c\u0628\u0647\u200c\u06af\u0627\u0645\u060c \u0645\u0647\u0627\u0631\u062a\u200c\u0647\u0627\u06cc \u0644\u0627\u0632\u0645 \u0628\u0631\u0627\u06cc \u067e\u06cc\u0627\u062f\u0647\u200c\u0633\u0627\u0632\u06cc \u06a9\u0627\u0645\u0644 \u06cc\u06a9 \u0645\u062f\u0627\u0631 \u062f\u06cc\u062c\u06cc\u062a\u0627\u0644 \u0631\u0648\u06cc FPGA \u0648 \u0637\u0631\u0627\u062d\u06cc \u067e\u0627\u06cc\u0647\u200c\u0647\u0627\u06cc \u0627\u0648\u0644\u06cc\u0647 \u062f\u0631 \u0641\u0631\u0622\u06cc\u0646\u062f ASIC \u0631\u0627 \u06a9\u0633\u0628 \u062e\u0648\u0627\u0647\u06cc\u062f \u06a9\u0631\u062f. \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647 \u0628\u0631\u0627\u06cc \u062f\u0627\u0646\u0634\u062c\u0648\u06cc\u0627\u0646 \u0645\u0647\u0646\u062f\u0633\u06cc \u0628\u0631\u0642 \u0648 \u0639\u0644\u0627\u0642\u0647\u200c\u0645\u0646\u062f\u0627\u0646 \u0628\u0647 \u0637\u0631\u0627\u062d\u06cc \u0633\u062e\u062a\u200c\u0627\u0641\u0632\u0627\u0631 \u0633\u0637\u062d \u0628\u0627\u0644\u0627 \u0645\u0646\u0627\u0633\u0628 \u0627\u0633\u062a.\n <\/p>\n<\/div>\n

\n

\u0627\u0647\u062f\u0627\u0641 \u06cc\u0627\u062f\u06af\u06cc\u0631\u06cc<\/h2>\n
    \n
  • \u062f\u0631\u06a9 \u0645\u0641\u0627\u0647\u06cc\u0645 \u067e\u0627\u06cc\u0647\u200c\u0627\u06cc \u0632\u0628\u0627\u0646 VHDL \u0648 \u0633\u0627\u062e\u062a\u0627\u0631\u0647\u0627\u06cc \u0646\u062d\u0648\u06cc \u0622\u0646.<\/li>\n
  • \u06cc\u0627\u062f\u06af\u06cc\u0631\u06cc \u0631\u0648\u0634\u200c\u0647\u0627\u06cc \u0645\u062f\u0644\u0633\u0627\u0632\u06cc \u0631\u0641\u062a\u0627\u0631\u06cc<\/span> \u0648 \u0633\u0627\u062e\u062a\u0627\u0631\u06cc<\/span> \u062f\u0631 VHDL.<\/li>\n
  • \u062a\u0648\u0627\u0646\u0627\u06cc\u06cc \u0646\u0648\u0634\u062a\u0646 Testbench \u0628\u0631\u0627\u06cc \u0634\u0628\u06cc\u0647\u200c\u0633\u0627\u0632\u06cc \u0631\u0641\u062a\u0627\u0631 \u0645\u062f\u0627\u0631.<\/li>\n
  • \u067e\u06cc\u0627\u062f\u0647\u200c\u0633\u0627\u0632\u06cc \u067e\u0631\u0648\u0698\u0647\u200c\u0647\u0627\u06cc \u0633\u0627\u062f\u0647 \u0631\u0648\u06cc \u0628\u0631\u062f FPGA.<\/li>\n
  • \u0622\u0634\u0646\u0627\u06cc\u06cc \u0628\u0627 \u0646\u06a9\u0627\u062a \u06a9\u0644\u06cc\u062f\u06cc \u0642\u0628\u0644 \u0627\u0632 \u0648\u0631\u0648\u062f \u0628\u0647 \u0641\u0631\u0622\u06cc\u0646\u062f ASIC<\/span> Design.<\/li>\n<\/ul>\n<\/div>\n
    \n

    \u0633\u0631\u0641\u0635\u0644\u200c\u0647\u0627 \u0648 \u0633\u0627\u062e\u062a\u0627\u0631 \u062f\u0648\u0631\u0647<\/h2>\n

    \n \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647 \u062f\u0631 \u0642\u0627\u0644\u0628 \u0647\u0641\u062a \u0641\u0635\u0644 \u0627\u0635\u0644\u06cc \u062a\u0646\u0638\u06cc\u0645 \u0634\u062f\u0647 \u0627\u0633\u062a. \u0647\u0631 \u0641\u0635\u0644 \u0634\u0627\u0645\u0644 \u0628\u062e\u0634\u200c\u0647\u0627\u06cc \u062a\u0626\u0648\u0631\u06cc\u060c \u0645\u062b\u0627\u0644\u200c\u0647\u0627\u06cc \u06a9\u0627\u0631\u0628\u0631\u062f\u06cc \u0648 \u062a\u0645\u0631\u06cc\u0646\u0627\u062a \u0639\u0645\u0644\u06cc \u0628\u0631\u0627\u06cc \u062a\u062b\u0628\u06cc\u062a \u0645\u0641\u0627\u0647\u06cc\u0645 \u0627\u0633\u062a:\n <\/p>\n

      \n
    • \u0641\u0635\u0644 \u0627\u0648\u0644: \u0645\u0641\u0627\u0647\u06cc\u0645 \u067e\u0627\u06cc\u0647\u200c\u0627\u06cc VHDL \u0648 \u0645\u0639\u0631\u0641\u06cc \u0627\u0633\u062a\u0627\u0646\u062f\u0627\u0631\u062f IEEE 1076<\/li>\n
    • \u0641\u0635\u0644 \u062f\u0648\u0645: \u0627\u0646\u0648\u0627\u0639 \u062f\u0627\u062f\u0647\u200c\u0647\u0627\u060c \u0633\u06cc\u06af\u0646\u0627\u0644\u200c\u0647\u0627 \u0648 \u0645\u062a\u063a\u06cc\u0631\u0647\u0627<\/li>\n
    • \u0641\u0635\u0644 \u0633\u0648\u0645: \u0645\u062f\u0644\u200c\u0633\u0627\u0632\u06cc \u0631\u0641\u062a\u0627\u0631\u06cc \u0648 \u0641\u0631\u0622\u06cc\u0646\u062f\u0647\u0627\u06cc \u0647\u0645\u0632\u0645\u0627\u0646<\/li>\n
    • \u0641\u0635\u0644 \u0686\u0647\u0627\u0631\u0645: \u0637\u0631\u0627\u062d\u06cc \u0633\u0627\u062e\u062a\u0627\u0631\u06cc \u0628\u0627 \u0645\u0648\u0644\u0641\u0647\u200c\u0647\u0627\u06cc \u0622\u0645\u0627\u062f\u0647<\/li>\n
    • \u0641\u0635\u0644 \u067e\u0646\u062c\u0645: \u0646\u0648\u0634\u062a\u0646 Testbench \u0648 \u0634\u0628\u06cc\u0647\u200c\u0633\u0627\u0632\u06cc \u0628\u0627 ModelSim<\/li>\n
    • \u0641\u0635\u0644 \u0634\u0634\u0645: \u067e\u06cc\u0627\u062f\u0647\u200c\u0633\u0627\u0632\u06cc \u0631\u0648\u06cc FPGA (\u0646\u0631\u0645\u200c\u0627\u0641\u0632\u0627\u0631 Vivado)<\/li>\n
    • \u0641\u0635\u0644 \u0647\u0641\u062a\u0645: \u0646\u06a9\u0627\u062a \u0648 \u0686\u0627\u0644\u0634\u200c\u0647\u0627\u06cc \u0627\u0648\u0644\u06cc\u0647 \u062f\u0631 \u0637\u0631\u0627\u062d\u06cc ASIC<\/li>\n<\/ul>\n

      \n \u062f\u0631 \u067e\u0627\u06cc\u0627\u0646 \u0647\u0631 \u0641\u0635\u0644\u060c \u06cc\u06a9 \u0622\u0632\u0645\u0648\u0646 \u06a9\u0648\u062a\u0627\u0647 \u0648 \u06cc\u06a9 \u067e\u0631\u0648\u0698\u0647 \u0639\u0645\u0644\u06cc \u0627\u0631\u0627\u0626\u0647 \u0645\u06cc\u200c\u0634\u0648\u062f \u062a\u0627 \u06cc\u0627\u062f\u06af\u06cc\u0631\u06cc \u0628\u0647\u200c\u0635\u0648\u0631\u062a \u0645\u0631\u062d\u0644\u0647\u200c\u0627\u06cc \u0628\u0631\u0631\u0633\u06cc \u0634\u0648\u062f.\n <\/p>\n<\/div>\n

      \n

      \u067e\u06cc\u0634\u200c\u0646\u06cc\u0627\u0632\u0647\u0627<\/h2>\n
        \n
      • \u0622\u0634\u0646\u0627\u06cc\u06cc \u0628\u0627 \u0645\u062f\u0627\u0631\u0647\u0627\u06cc \u0645\u0646\u0637\u0642\u06cc \u062f\u06cc\u062c\u06cc\u062a\u0627\u0644<\/span> \u0648 \u062f\u0631\u06a9 \u0645\u0641\u0627\u0647\u06cc\u0645 AND\u060c OR\u060c Flip-Flop \u0648 \u063a\u06cc\u0631\u0647.<\/li>\n
      • \u0645\u0628\u0627\u0646\u06cc \u0632\u0628\u0627\u0646 \u0628\u0631\u0646\u0627\u0645\u0647\u200c\u0646\u0648\u06cc\u0633\u06cc (\u062a\u0631\u062c\u06cc\u062d\u0627\u064b C \u06cc\u0627 Python) \u0628\u0631\u0627\u06cc \u062f\u0631\u06a9 \u0633\u0627\u062e\u062a\u0627\u0631\u0647\u0627\u06cc \u0634\u0631\u0637\u06cc \u0648 \u062d\u0644\u0642\u0647\u200c\u0647\u0627.<\/li>\n
      • \u0646\u0635\u0628 \u0646\u0631\u0645\u200c\u0627\u0641\u0632\u0627\u0631\u0647\u0627\u06cc ModelSim \u0648 Vivado (\u0646\u0633\u062e\u0647 \u0622\u0632\u0645\u0648\u0646 \u06cc\u0627 Academic) \u0631\u0648\u06cc \u0633\u06cc\u0633\u062a\u0645 \u0634\u062e\u0635\u06cc.<\/li>\n<\/ul>\n

        \n \u0627\u06af\u0631 \u062a\u062c\u0631\u0628\u0647\u0654 \u0642\u0628\u0644\u06cc \u0628\u0627 \u0632\u0628\u0627\u0646\u200c\u0647\u0627\u06cc HDL \u0646\u062f\u0627\u0631\u06cc\u062f\u060c \u067e\u06cc\u0634\u0646\u0647\u0627\u062f \u0645\u06cc\u200c\u0634\u0648\u062f \u0627\u0628\u062a\u062f\u0627 \u0628\u0627 \u06cc\u06a9 \u062f\u0648\u0631\u0647\u0654 \u0645\u0642\u062f\u0645\u0627\u062a\u06cc \u0645\u062f\u0627\u0631 \u0645\u0646\u0637\u0642\u06cc \u06cc\u0627 \u0632\u0628\u0627\u0646 Verilog \u0622\u0634\u0646\u0627 \u0634\u0648\u06cc\u062f. \u0627\u0645\u0627 \u0628\u0627 \u062d\u062f\u0627\u0642\u0644 \u062f\u0627\u0646\u0634 \u06af\u0641\u062a\u0647\u200c\u0634\u062f\u0647 \u0647\u0645 \u0645\u06cc\u200c\u062a\u0648\u0627\u0646\u06cc\u062f \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647 \u0631\u0627 \u0628\u0647 \u062e\u0648\u0628\u06cc \u062f\u0646\u0628\u0627\u0644 \u06a9\u0646\u06cc\u062f.\n <\/p>\n<\/div>\n

        \n

        \u0645\u0632\u0627\u06cc\u0627\u06cc \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647<\/h2>\n
          \n
        • \u0633\u0628\u06a9 \u0622\u0645\u0648\u0632\u0634\u06cc \u06af\u0627\u0645 \u0628\u0647 \u06af\u0627\u0645<\/span> \u0648 \u067e\u0631\u0648\u0698\u0647\u200c\u0645\u062d\u0648\u0631 \u0645\u0646\u0627\u0633\u0628 \u0628\u0631\u0627\u06cc \u0645\u0628\u062a\u062f\u06cc\u0627\u0646 \u0648 \u0645\u062a\u0648\u0633\u0637\u200c\u0647\u0627.<\/li>\n
        • \u0641\u0631\u0627\u0647\u0645 \u0634\u062f\u0646 \u062f\u0633\u062a\u0631\u0633\u06cc \u0628\u0647 \u0641\u0627\u06cc\u0644\u200c\u0647\u0627\u06cc \u067e\u0631\u0648\u0698\u0647 \u0648 \u0645\u062b\u0627\u0644\u200c\u0647\u0627\u06cc \u06a9\u0627\u0645\u0644 \u0628\u0631\u0627\u06cc \u062a\u0645\u0631\u06cc\u0646 \u0628\u06cc\u0634\u062a\u0631.<\/li>\n
        • \u0622\u0645\u0648\u0632\u0634 \u0627\u0633\u062a\u0631\u0627\u062a\u0698\u06cc\u200c\u0647\u0627\u06cc \u0628\u0647\u06cc\u0646\u0647\u200c\u0633\u0627\u0632\u06cc \u0645\u0635\u0631\u0641 \u0645\u0646\u0627\u0628\u0639 FPGA \u0648 \u06a9\u0627\u0647\u0634 \u0647\u0632\u06cc\u0646\u0647 \u062f\u0631 \u0637\u0631\u0627\u062d\u06cc ASIC.<\/li>\n
        • \u06cc\u0627\u062f\u06af\u06cc\u0631\u06cc \u0646\u062d\u0648\u0647\u0654 \u062a\u0648\u0644\u06cc\u062f Testbench<\/span> \u0647\u0627\u06cc \u0627\u0633\u062a\u0627\u0646\u062f\u0627\u0631\u062f \u0628\u0631\u0627\u06cc \u0634\u0628\u06cc\u0647\u200c\u0633\u0627\u0632\u06cc \u0645\u0639\u062a\u0628\u0631.<\/li>\n
        • \u0627\u0645\u06a9\u0627\u0646 \u0627\u0633\u062a\u0641\u0627\u062f\u0647 \u0627\u0632 \u0645\u062f\u0631\u06a9 \u067e\u0627\u06cc\u0627\u0646 \u062f\u0648\u0631\u0647 \u0628\u0631\u0627\u06cc \u0627\u0631\u0627\u0626\u0647 \u062f\u0631 \u0631\u0632\u0648\u0645\u0647 \u0648 \u067e\u0631\u0648\u0641\u0627\u06cc\u0644 \u0644\u06cc\u0646\u06a9\u062f\u06cc\u0646.<\/li>\n<\/ul>\n<\/div>\n
          \n

          \u06cc\u0627\u062f\u06af\u06cc\u0631\u06cc \u0639\u0645\u0644\u06cc \u0628\u0627 \u0645\u062b\u0627\u0644<\/h2>\n

          \n \u062f\u0631 \u0628\u062e\u0634 \u0639\u0645\u0644\u06cc \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647\u060c \u0627\u0628\u062a\u062f\u0627 \u06cc\u06a9 \u0645\u062f\u0627\u0631 \u0633\u0627\u062f\u0647\u0654 \u0634\u0645\u0627\u0631\u0646\u062f\u0647 \u06f4 \u0628\u06cc\u062a\u06cc \u0631\u0627 \u0627\u0632 \u0635\u0641\u0631 \u062a\u0627 \u0635\u062f \u062f\u0631 VHDL \u0645\u06cc\u200c\u0646\u0648\u06cc\u0633\u06cc\u0645\u060c \u0634\u0628\u06cc\u0647\u200c\u0633\u0627\u0632\u06cc \u0645\u06cc\u200c\u06a9\u0646\u06cc\u0645 \u0648 \u0633\u067e\u0633 \u0631\u0648\u06cc \u0628\u0631\u062f FPGA \u0627\u062c\u0631\u0627 \u0645\u06cc\u200c\u06a9\u0646\u06cc\u0645. \u0645\u062b\u0627\u0644 \u06a9\u062f \u0627\u0648\u0644\u06cc\u0647 \u0628\u0631\u0627\u06cc \u062a\u0639\u0631\u06cc\u0641 \u0633\u06cc\u06af\u0646\u0627\u0644 \u0633\u0627\u0639\u062a \u0628\u0647\u200c\u0635\u0648\u0631\u062a \u0632\u06cc\u0631 \u0627\u0633\u062a:\n <\/p>\n

          \n
          \n architecture Behavioral of Counter4bit is
          \n signal clk_div : std_logic := ‘0’;
          \n begin
          \n process(clk)
          \n begin
          \n if rising_edge(clk) then
          \n clk_div <= not clk_div; \n end if; \n end process; \n end Behavioral;\n <\/span>\n <\/p>\n

          \n \u067e\u0633 \u0627\u0632 \u0622\u0634\u0646\u0627\u06cc\u06cc \u0628\u0627 \u0627\u06cc\u0646 \u0645\u062b\u0627\u0644 \u0633\u0627\u062f\u0647\u060c \u0628\u0647 \u0633\u0645\u062a \u0637\u0631\u0627\u062d\u06cc \u0648\u0627\u062d\u062f \u0622\u0631\u06cc\u062a\u0645\u062a\u06cc\u06a9 (ALU)\u060c \u062d\u0627\u0641\u0638\u0647 FIFO \u0648 \u0645\u062f\u0648\u0644\u0627\u062a\u0648\u0631 \u062f\u06cc\u062c\u06cc\u062a\u0627\u0644 \u062d\u0631\u06a9\u062a \u0645\u06cc\u200c\u06a9\u0646\u06cc\u0645. \u0647\u0631 \u067e\u0631\u0648\u0698\u0647 \u0634\u0627\u0645\u0644 \u0641\u0627\u06cc\u0644 VHDL\u060c Testbench \u0648 \u0627\u0633\u06a9\u0631\u06cc\u067e\u062a \u0634\u0628\u06cc\u0647\u200c\u0633\u0627\u0632\u06cc \u0627\u0633\u062a \u062a\u0627 \u0645\u0637\u0627\u0628\u0642 \u0627\u0633\u062a\u0627\u0646\u062f\u0627\u0631\u062f\u0647\u0627\u06cc \u0635\u0646\u0639\u062a\u06cc \u0639\u0645\u0644 \u06a9\u0646\u06cc\u062f.\n <\/p>\n

          \n \u062f\u0631 \u0646\u0647\u0627\u06cc\u062a\u060c \u06cc\u06a9 \u067e\u0631\u0648\u0698\u0647\u0654 \u06a9\u0627\u0645\u0644 \u067e\u0646\u062c \u0628\u062e\u0634\u06cc \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc \u06cc\u06a9 \u0633\u06cc\u0633\u062a\u0645 \u0627\u0631\u062a\u0628\u0627\u0637 \u0633\u0631\u06cc\u0627\u0644 UART \u0645\u0639\u0631\u0641\u06cc \u0645\u06cc\u200c\u0634\u0648\u062f \u062a\u0627 \u0628\u062a\u0648\u0627\u0646\u06cc\u062f \u062f\u0631 \u0645\u062d\u06cc\u0637 FPGA \u067e\u06cc\u0627\u062f\u0647\u200c\u0633\u0627\u0632\u06cc \u0648 \u0622\u0632\u0645\u0627\u06cc\u0634\u200c\u0647\u0627\u06cc \u0639\u0645\u0644\u06a9\u0631\u062f\u06cc \u0631\u0627 \u0627\u0646\u062c\u0627\u0645 \u062f\u0647\u06cc\u062f.\n <\/p>\n<\/div>\n

          \n

          \u0646\u062a\u06cc\u062c\u0647\u200c\u06af\u06cc\u0631\u06cc<\/h2>\n

          \n \u0628\u0627 \u06af\u0630\u0631\u0627\u0646\u062f\u0646 \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647\u060c \u062f\u0627\u0646\u0634 \u06a9\u0627\u0645\u0644\u06cc \u0627\u0632 \u0632\u0628\u0627\u0646 VHDL \u0648 \u0641\u0631\u0622\u06cc\u0646\u062f \u0637\u0631\u0627\u062d\u06cc \u062f\u06cc\u062c\u06cc\u062a\u0627\u0644 \u06a9\u0633\u0628 \u0645\u06cc\u200c\u06a9\u0646\u06cc\u062f. \u0634\u0645\u0627 \u0642\u0627\u062f\u0631 \u062e\u0648\u0627\u0647\u06cc\u062f \u0628\u0648\u062f \u0627\u0632 \u0627\u0628\u062a\u062f\u0627 \u06cc\u06a9 \u0645\u062f\u0627\u0631 \u0645\u0646\u0637\u0642\u06cc \u0631\u0627 \u0645\u062f\u0644\u200c\u0633\u0627\u0632\u06cc\u060c \u0634\u0628\u06cc\u0647\u200c\u0633\u0627\u0632\u06cc \u0648 \u062f\u0631 \u0646\u0647\u0627\u06cc\u062a \u0631\u0648\u06cc \u0633\u062e\u062a\u200c\u0627\u0641\u0632\u0627\u0631 \u0648\u0627\u0642\u0639\u06cc (FPGA \u06cc\u0627 ASIC) \u067e\u06cc\u0627\u062f\u0647\u200c\u0633\u0627\u0632\u06cc \u06a9\u0646\u06cc\u062f. \u0627\u06cc\u0646 \u0645\u0647\u0627\u0631\u062a\u200c\u0647\u0627 \u062f\u0631 \u0628\u0627\u0632\u0627\u0631 \u06a9\u0627\u0631 \u0645\u0647\u0646\u062f\u0633\u06cc \u0633\u062e\u062a\u200c\u0627\u0641\u0632\u0627\u0631\u060c \u0637\u0631\u0627\u062d\u06cc SoC \u0648 \u062a\u0648\u0633\u0639\u0647 \u0633\u06cc\u0633\u062a\u0645\u200c\u0647\u0627\u06cc \u0646\u0647\u0641\u062a\u0647 \u0628\u0633\u06cc\u0627\u0631 \u06a9\u0627\u0631\u0628\u0631\u062f\u06cc \u0647\u0633\u062a\u0646\u062f.\n <\/p>\n

          \n \u0647\u0645\u200c\u0627\u06a9\u0646\u0648\u0646<\/span> \u0627\u06cc\u0646 \u062f\u0648\u0631\u0647 \u0631\u0627 \u062f\u0627\u0646\u0644\u0648\u062f \u06a9\u0646\u06cc\u062f \u0648 \u0645\u0633\u06cc\u0631 \u062d\u0631\u0641\u0647\u200c\u0627\u06cc \u062e\u0648\u062f \u0631\u0627 \u062f\u0631 \u0632\u0645\u06cc\u0646\u0647 \u0637\u0631\u0627\u062d\u06cc \u0633\u062e\u062a\u200c\u0627\u0641\u0632\u0627\u0631 \u0628\u0627 VHDL \u0622\u063a\u0627\u0632 \u0646\u0645\u0627\u06cc\u06cc\u062f!\n <\/p>\n<\/div>\n<\/article>\n","protected":false},"excerpt":{"rendered":"

          \u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0627\u0646\u06af\u0644\u06cc\u0633\u06cc \u062f\u0627\u0646\u0644\u0648\u062f Introduction to VHDL for FPGA and ASIC design \u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0641\u0627\u0631\u0633\u06cc \u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f […]<\/p>\n","protected":false},"featured_media":67493,"comment_status":"open","ping_status":"closed","template":"","meta":{"pmpro_default_level":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}}},"product_cat":[1225],"product_tag":[27959,27954,27956,27952,7984,27953,7982,27951,7988,27948,27955,27957,7981,27958,7972,27949,18336,27946,27945,27950,27947,16204,27944],"class_list":{"0":"post-102710","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-1225","7":"product_tag-altera-vhdl","8":"product_tag-asic-design","9":"product_tag-asic-development","10":"product_tag-asic-","11":"product_tag-digital-design","12":"product_tag-fpga-design","13":"product_tag-fpga-development","14":"product_tag-fpga-","15":"product_tag-hardware-description-language","16":"product_tag-hdl","17":"product_tag-hdl-programming","18":"product_tag-programmable-logic","19":"product_tag-vhdl-tutorial","20":"product_tag-xilinx-vhdl","21":"product_tag--vhdl","22":"product_tag-27949","23":"product_tag-18336","24":"product_tag--asic","25":"product_tag--fpga","26":"product_tag-27950","28":"product_tag-16204","29":"product_tag---vhdl","30":"pmpro-has-access","31":"desktop-align-left","32":"tablet-align-left","33":"mobile-align-left","35":"first","36":"instock","37":"shipping-taxable","38":"purchasable","39":"product-type-variable"},"yoast_head":"\n\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC - 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\u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633\",\"isPartOf\":{\"@id\":\"https:\/\/express24.ir\/d\/#website\"},\"datePublished\":\"2025-05-27T20:03:24+00:00\",\"dateModified\":\"2025-05-27T20:03:26+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/#breadcrumb\"},\"inLanguage\":\"fa-IR\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"\u062e\u0627\u0646\u0647\",\"item\":\"https:\/\/express24.ir\/d\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"\u0641\u0631\u0648\u0634\u06af\u0627\u0647\",\"item\":\"https:\/\/express24.ir\/d\/\"},{\"@type\":\"ListItem\",\"position\":3,\"name\":\"\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/express24.ir\/d\/#website\",\"url\":\"https:\/\/express24.ir\/d\/\",\"name\":\"\u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633\",\"description\":\"\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/express24.ir\/d\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"fa-IR\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC - \u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/express24.ir\/d\/product\/\u062f\u0627\u0646\u0644\u0648\u062f-\u062f\u0648\u0631\u0647-\u062f\u0627\u0646\u0644\u0648\u062f-\u0645\u0642\u062f\u0645\u0647\u0627\u06cc-\u0628\u0631-vhdl-\u0628\u0631\u0627\u06cc-\u0637\/","og_locale":"fa_IR","og_type":"article","og_title":"\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC - \u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633","og_description":"\u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0627\u0646\u06af\u0644\u06cc\u0633\u06cc \u062f\u0627\u0646\u0644\u0648\u062f Introduction to VHDL for FPGA and ASIC design \u0646\u0627\u0645 \u0645\u062d\u0635\u0648\u0644 \u0628\u0647 \u0641\u0627\u0631\u0633\u06cc \u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f […]","og_url":"https:\/\/express24.ir\/d\/product\/\u062f\u0627\u0646\u0644\u0648\u062f-\u062f\u0648\u0631\u0647-\u062f\u0627\u0646\u0644\u0648\u062f-\u0645\u0642\u062f\u0645\u0647\u0627\u06cc-\u0628\u0631-vhdl-\u0628\u0631\u0627\u06cc-\u0637\/","og_site_name":"\u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633","article_modified_time":"2025-05-27T20:03:26+00:00","og_image":[{"width":1024,"height":1024,"url":"https:\/\/express24.ir\/d\/wp-content\/uploads\/2025\/05\/Express24_ir.png","type":"image\/png"}],"twitter_card":"summary_large_image","schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/","url":"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/","name":"\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC - \u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633","isPartOf":{"@id":"https:\/\/express24.ir\/d\/#website"},"datePublished":"2025-05-27T20:03:24+00:00","dateModified":"2025-05-27T20:03:26+00:00","breadcrumb":{"@id":"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/#breadcrumb"},"inLanguage":"fa-IR","potentialAction":[{"@type":"ReadAction","target":["https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/express24.ir\/d\/product\/%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d8%af%d9%88%d8%b1%d9%87-%d8%af%d8%a7%d9%86%d9%84%d9%88%d8%af-%d9%85%d9%82%d8%af%d9%85%d9%87%d8%a7%db%8c-%d8%a8%d8%b1-vhdl-%d8%a8%d8%b1%d8%a7%db%8c-%d8%b7\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"\u062e\u0627\u0646\u0647","item":"https:\/\/express24.ir\/d\/"},{"@type":"ListItem","position":2,"name":"\u0641\u0631\u0648\u0634\u06af\u0627\u0647","item":"https:\/\/express24.ir\/d\/"},{"@type":"ListItem","position":3,"name":"\u062f\u0627\u0646\u0644\u0648\u062f \u062f\u0648\u0631\u0647 \u062f\u0627\u0646\u0644\u0648\u062f \u0645\u0642\u062f\u0645\u0647\u200c\u0627\u06cc \u0628\u0631 VHDL \u0628\u0631\u0627\u06cc \u0637\u0631\u0627\u062d\u06cc FPGA \u0648 ASIC"}]},{"@type":"WebSite","@id":"https:\/\/express24.ir\/d\/#website","url":"https:\/\/express24.ir\/d\/","name":"\u0641\u0631\u0648\u0634\u06af\u0627\u0647 \u0627\u06a9\u0633\u067e\u0631\u0633","description":"","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/express24.ir\/d\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"fa-IR"}]}},"_links":{"self":[{"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/product\/102710","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/types\/product"}],"replies":[{"embeddable":true,"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/comments?post=102710"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/media\/67493"}],"wp:attachment":[{"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/media?parent=102710"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/product_cat?post=102710"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/express24.ir\/d\/wp-json\/wp\/v2\/product_tag?post=102710"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}